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XR-T7288 ...the analog plus company tm cept1 line interface rev. 1.01 1992 exar corporation, 48720 kato road, fremont, ca 94538 (510) 668-7000 fax (510) 668-7017 1 june 1997-3 features fully integrated 2.048mbits/s line interface intended for use in systems that must comply with ccitt specifications g.703, g.823, i.431, g.732, g.735, g.739 pin-selectable 75 w or 120 w operation monolithic clock recovery low power dissipation: 100mw for 120 w twisted pair, typical 108mw for 75 w coaxial, typical minimal external circuitry required robust frequency acquisition/phase-locked loop pin-selectable hdb3 encoder and decoder loopback modes for fault isolation multiple link-status and alarm features single-rail/dual-rail interface general description the XR-T7288 cept1 line interface is an integrated circuit that provides a 2.048 mbits/s line interface to either twisted-pair or coaxial cable as specified in ccitt requirements g.703, g.823, i.431, g.732, and g.735 g.739. the device performs receive pulse regeneration, timing recovery, and transmit pulse driving functions. the XR-T7288 device is manufactured by using low-power cmos technology and is available in a 28-pin, plastic dip or in a 28-pin, plastic soj package for surface mounting. the XR-T7288 device is functionally compatible with the lc1135b device. the digital circuitry is shown in figure 1. ; the analog circuitry is shown in figure 6. ordering information part no. package operating temperature range XR-T7288ip 28 lead 300 mil pdip -40 c to +85 c XR-T7288iw 28 lead 300 mil jedec soj -40 c to +85 c
XR-T7288 2 rev. 1.01 blue signal (ais) generator ??? ??? loss of clock detection ?? ?? ?? ?? ?? ?? ???? ???? blue (ais) signal generator ?? ?? ?? ?? ?? ?? bipolar violation detection ??? ??? ??? ??? dual - to single rail converter ??? ??? ??? single-to dual rail converter ?? ?? ?? ?? ?? hdb3 code violation detection ?? ?? ? ? ? ? ? ??? ??? ??? hdb3 encoder ? ? ? ? ? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ? ? ? ? ? ? ? transmit receive hdb3 decoder sr /dr hdb3/tndata sd los lp1 loc lp3 hdb3/tndata rbc sr /dr flm rdata/ rpdata vio/ rndata rclk tdata/ tpdata hdb3/ tndata tclk all analog functions +5 output drivers and logic +5 output drivers and logic gnd gnd all analog functions gnda gndd v dd d v dd a almt bclk tbc lp2 zs r2 t2 r1 t1 mux mux mux mux mux mux mux mux mux mux mux mux mux mux mux mux mux mux mux figure 1. digital block diagram
XR-T7288 3 rev. 1.01 pin configuration 28 lead soj (jedec, 0.300o) t1 r1 sd gnda v dd a zs t2 v dd d los loc hdb3/tndata vio/rndata rclk rdata/rpdata tclk tdata/tpdata r2 lp1 gndd lp2 nc lp3 flm almt sr /dr rbc bclk tbc 28 lead pdip (0.300o) 13 16 14 15 1 2 3 4 5 6 7 8 9 10 28 27 26 25 24 23 22 21 20 19 11 18 12 17 28 1 15 14 2 3 4 5 6 7 17 16 8 9 19 18 10 11 23 22 21 20 27 26 25 24 12 13 t1 r1 sd gnda v dd a zs t2 v dd d r2 gndd nc flm sr /dr bclk los loc hdb3/tndata vio/rndata rclk rdata/rpdata tclk tdata/tpdata lp1 lp2 lp3 almt rbc tbc pin description pin # symbol type description 1 los o loss of signal (active-low). this pin is cleared (0) upon loss of the data signal at the re- ceiver inputs. 2 loc o loss of clock (active-low). this pin is cleared when sd = 1 and los = 0, indicating that a loss of clock has occurred. when loc = 0, no transitions occur on the rclk and on either rdata (for single-rail) or rpdata and rndata (for dual-rail operation) outputs. a valid clock must be present at bclk for this function to operate properly. 3 hdb3/ tndata i hdb3 enable/n-rail transmit data. if sr /dr = 0, this pin is set (1) to insert an hdb3 sub- stitution code on the transmit side and to remove the substitution code on the receive side. if sr /dr = 1, this pin is used as the n-rail transmit input data (internal pull-down is included). 4 vio/ rndata o violation/n-rail receive data. if sr /dr = 0 and hdb3 = 0, bipolar violations on the re- ceive side input are detected, causing vio to be set; if hdb3 = 1, hdb3 code violations cause vio to be set. if sr /dr =1, this pin is used as the n-rail receive output data. 5 rclk o receive clock. output receive clock signal to the terminal equipment. 6 rdata/ rpdata o receive data/p-rail receive data. if sr /dr = 0, this pin is used for 2.048 mbits/s unipo- lar output data with a 100% duty cycle. if sr /dr = 1, this pin is used as the p-rail receive output data. 7 tclk i transmit clock. input clock signal (2.048 mhz 80 ppm). 8 tdata/ tpdata i transmit data/p-rail transmit data. if sr /dr = 0, this pin is used as 2.048 mbits/s unipo- lar input data. if sr /dr = 1, this pin is used as the p-rail transmit input data. 9 lp1 i loopback 1 enable (active-low). this pin is cleared for a full local loopback (transmit con- verter output to receive converter input). most of the transmit and receive analog circuitry is exercised in this loopback (internal pull-up is included). 10 lp2 i loopback 2 enable (active-low). this pin is cleared for a remote loopback. in loopback 2, a high on tbc (pin 14) inserts the blue signal (ais) on the transmit side (internal pull-up is included).
XR-T7288 4 rev. 1.01 pin description (cont'd) pin # symbol type description 11 lp3 i loopback 3 enable (active-low). this pin is cleared for a digital local loopback. only the transmit and receive digital sections are exercised in this loopback (internal pull-up is in- cluded). 12 almt i alarm test enable (active-low). this pin is cleared, forcing los = 0, loc = 0, and vio = 1 for testing without affecting data transmission (internal pull-up is included). 13 rbc i receive blue control. this pin is set to insert the blue signal (ais) on the receive side (in- ternal pull-down is included). 14 tbc i transmit blue control. this pin is set to insert the blue signal (ais) on the transmit side. this control has priority over a loopback 2 if both are operated (internal pull-down is included). 15 bclk i blue clock. blue clock (ais) input signal (2.048mhz 80ppm). this clock can be indepen- dent of the transmit clock. 16 sr /dr i single-rail (active-low)/dual-rail operation. if sr /dr = 0 (internal pull-down is in- cluded), single-rail operation is selected; if sr /dr = 1, dual-rail operation is selected ( see tables 3-5 ). 17 flm i framer logic mode. if flm = 0 (internal pull-down is included), logic mode 1 operation oc- curs. if flm = 1, logic mode 2 operation occurs ( see tables 3-5 ). 18 nc no connection. test pin for manufacturing purposes only. this pin must be left floating or tied to gndd. 19 gndd digital ground. 20 r2 o transmit bipolar ring. negative bipolar transmit output. 21 v dd d 5v digital supply ( 10%). 22 t2 o transmit bipolar tip. positive bipolar transmit output. 23 zs i impedance select. this pin is cleared for 75 w coaxial cable operation and set for 120 w shielded twisted-pair operation (internal pull-down is included) 24 v dd a 5v analog supply ( 10%). 25 gnda analog ground. 26 sd i shutdown enable. if this pin is high, a loss-of-signal detection (los = 0) forces loc low and causes the following (see table 2 ): for single-rail operation: rclk high, rdata low. for dual-rail, logic mode 1 operation rclk high, rpdata and rndata low. for dual-rail, logic mode 2 operation: rclk low, rpdata and rndata high (internal pull- down is included). 27 r1 i receive bipolar ring. negative bipolar receive input 28 t1 i receive bipolar tip. positive bipolar receive input.
XR-T7288 5 rev. 1.01 electrical characteristics test conditions: t a = -40 c to +85 c; v dd = 5v 10% symbol parameter min. typ. max. unit conditions logic interface electrical characteristics input voltage v il low gndd 0.8 v v ih high 2.0 v dd d v output voltage 1 v ol low gndd 0.4 v 2.0ma sink v oh high 2.4 v dd d v 80 m a source c i input capacitance 20 pf c l load capacitance 40 pf transmitter specifications output pulse amplitude 75 w (zs = 0) 2.14 2.37 2.60 v 120 w (zs = 1) 2.70 3.00 3.30 v pulse width (50%) 219 244 269 ns positive/negative pulse imbalance 5 % zero level 10 2 % 2 output transformer turns ratio 1:1.33 1:1.36 1:1.39 receiver specifications receiver sensitivity 3 0.7 4.2 vp allowed cable loss at ber 10 -9 no interference 10 7 db interfering pbrs, 18db 6 db below transmitted pbrs pll 4 3db bandwidth 28 khz peaking 0.24 0.5 db ico free-running frequency error 7 % notes 1 digital outputs drive purely capacitive loads to full output levels (v dd d, gndd) 2 percentage of the nominal pulse amplitude. 3 measured at t1, r1 (v peak-to-zero, gnd reference) 4 transfer characteristics (1/4 input) 5 all measurements are with a matched-impedance transmit interface (see figure 3. and figure 4.) and with v dd or gnd applied to digital input leads. internal pull-up devices are provided on the following input leads: lp1 , lp2 , lp3 and almt . internal pull-down devices are provided on the following leads: sd, rbc, hdb3/tndata, tbc, sr /dr, flm, and zs. the internal pull-up or pull-down devices require the input to source or sink to be no more than 20 m a. specifications are subject to change without notice
XR-T7288 6 rev. 1.01 electrical characteristics (cont'd) symbol parameter min. typ. max. unit conditions receiver specifications (cont'd) input transformer turns ratio 1:1.9 1:2.0 1:2.1 input resistance, ri or ti, each input to ground 0.9 3.0 k w jitter (20hz-100khz) receive plus transmit jitter at t2/r2 0.06 0.09 u.i. peak-to-peak transmit jitter at t2/r2 0.012 0.04 u.i. peak-to-peak power dissipation 5 (ta=-40 c to +85 c, v dd =5.0 v 10%) power dissipation pdis 75 (zs = 0) 190 290 mw all 1s transmit and pdis 120 (zs = 1) 170 260 mw receive data, v dd =5.5v power dissipation: pdis 75 (zs = 0) 170 mw all 1s transmit and pdis 120 (zs = 1) 150 mw receive data, v dd =5.0v power dissipation: pdis 75 (zs = 0) 108 mw prbs (50% 1s) transmit and pdis 120 (zs = 1) 100 mw receive data, v dd =5.0v notes 1 digital outputs drive purely capacitive loads to full output levels (v dd d, gndd) 2 percentage of the nominal pulse amplitude. 3 measured at t1, r1 (v peak-to-zero, gnd reference) 4 transfer characteristics (1/4 input) 5 all measurements are with a matched-impedance transmit interface (see figure 3. and figure 4.) and with v dd or gnd applied to digital input leads. internal pull-up devices are provided on the following input leads: lp1 , lp2 , lp3 and almt . internal pull-down devices are provided on the following leads: sd, rbc, hdb3/tndata, tbc, sr /dr, flm, and zs. the internal pull-up or pull-down devices require the input to source or sink to be no more than 20 m a. specifications are subject to change without notice absolute maximum ratings dc supply voltage (v dd ) -0.5v to +6.5v . . . . . . . . . . . power dissipation (pdis) 500mw . . . . . . . . . . . . . . . . . storage temperature (tstg) -65 c to +125 c . . . . . . . maximum voltage (any pin) with respect to v dd 0.5v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . minimum voltage (any pin) with respect to gnd -0.5v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . maximum allowable voltages (t1, r1) with respect to gnd -5.0v to 5.0v . . . . . . stresses in excess of the absolute maximum ratings can cause permanent damage to the device. these are absolute stress ratings only. functional operation of the device is not implied at these or any other conditions in excess of those given in the opera tion sec- tions of the data sheet. exposure to absolute maximum ratings for extended periods can adversely affect device reliability. pin assignment ordering information
XR-T7288 7 rev. 1.01 v cc 8 9 rp5h 330 7 10 rp5g l5 vio/rdata l1 bl tp1 xtalout 11 10 q2e 04 13 12 q2f 04 bl xtal1 8.192mhz v cc 2 rrpos 15 rclk 4 rrclk 13 rneg 3 rrneg 14 bl 11 xtal2 10 xtal1 9 xtal 7 dja 1 bds 5 test 6 rst 12 gnd 8 q3 2188 (jitter attenuator) 2 1 3 j8 2 1 3 j6 2 1 3 j7 rpos rrpos rneg rclk rrclk 1 2 b5 rndata 1 2 b6 rclk 1 2 b4 rpdata rrneg hdb3 v cc 1 1 6 rp2a 10k 1 2 b8 tndata 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 sw1 on 2 1 5 1 1 6 rp4a 10k rpdata 6 rclk 5 rndata 4 tndata 3 lp1 9 lp3 10 lp3 11 almt 12 rbc 13 tbc 14 tpdata 8 tclk 7 bclk 15 v cc d 21 v cc a 24 gnda 25 gndd 19 nc 18 sr/dr 16 zs 23 sd 26 flm 17 loc 2 los 1 t1 28 r1 27 t2 22 r2 20 q1 XR-T7288 rst bds test dja flm sd zs 3 1 4 4 1 3 5 1 2 6 1 1 7 1 0 8 9 1 2 q2a 04 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 sw2 on srdr 3 14 rp5c 330 l3 loc r16 200 5 12 rp5e 330 t2 pe-65415 2:1 1 2 b3 rxin l2 los r8 270 r2 866 2 1 3 j4 r5 270 r3 866 2 1 3 j3 twp twp coax coax r13 26.1 2 1 3 j2 3 4 q2b 04 7 1 0 8 9 loc los v cc 2 1 5 rp2b 10k 3 1 4 4 1 3 5 1 2 6 1 1 tpdata 1 2 b7 rpdata 2 1 3 j5 ext tclk r17 75 1 2 b9 tclk 1 2 b1 blue clock bclk v cc c2 0.1uf r14 15.4 twp coax twp coax 2 1 3 j1 r11 26.1 r15 15.4 e1 22uf c1 0.1uf t1 pe-64937 1:1.36 1 16 rp5a 330 1 2 b2 txout l4 pwr 1 p1 v cc 1 p2 gnd figure 2. suggested application circuit v cc 16 rpos
XR-T7288 8 rev. 1.01 system description the XR-T7288 device is a fully integrated line interface that requires only two transformers, three input termination resistors, and two output impedance-matching resistors to provide a bidirectional line interface between a 2.048 mbits/s cept datalink and terminal equipment. typical application diagrams are shown in figure 3. and figure 4. for 75 w coaxial cable and 120 w shielded twisted-pair operation, respectively. the circuit is divided into three main blocks: transmit converter, receive converter, and logic. the transmit and receive converters process information signals through the device in the transmit and receive directions, respectively; the logic is the control and status interface for the device. figure 3. and figure 4. include a matched-impedance transmit-interface section in order to match the output impedance of the transmitter to the line. see table 1 for the g.703/ch-ptt specifications for transmit-interface return loss. ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ? ? ? ? ?? ?? ?? ?? ?? ?? ? ? ? ? ? transmit output t2 r2 15.4 w tclk hdb3/tndata tdata/tpdata gnda gndd XR-T7288 cept1 line interface zs v dd a v dd d rclk vio/rndata rdata/rpdata receive input t1 r1 15.4 w load 1.36:1 75 w transmitted data matched-impedance transmit interface 270 w 200 w +5v 1 m f 270 w 1:2 ?? ?? ?? ?? ?? ?? ??? ??? ??? ??? receive data ?? figure 3. typical application diagram for coaxial environment
XR-T7288 9 rev. 1.01 ? ? ? ? ? ? ? ? ? ? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? transmit output t2 r2 26.1 w tclk hdb3/tndata tdata/tpdata gnda gndd XR-T7288 cept1 line interface zs v dd a v dd d rclk vio/rndata rdata/rpdata receive input t1 r1 26.1 w load 1.36:1 120 w transmitted data matched-impedance transmit interface 200 w +5v 1 m f 866 w 1:2 receive data 866 w figure 4. typical application diagram for shielded twisted-pair environment interface min typ max units transmit 51 khz to 102 khz 8 28 db 102 khz to 2.048 mhz 14 26 db 2.048 mhz to 3.072 mhz 10 24 db receive 51 khz to 102 khz 12 32 db 102 khz to 2.048 mhz 18 31 db 2.048 mhz to 3.072 mhz 14 30 db table 1. return loss (resistor tolerance: 1% on transmit side, 2% on receive side)
XR-T7288 10 rev. 1.01 transmit converter the line-interface transmission format is return-to-zero, bipolar alternate mark inversion (ami), requiring transmission and sensing of alternately positive and negative pulses. the transmit converter accepts unipolar data and clock and converts the signal to a balanced bipolar data signal. binary 1s in the data stream become pulses of alternating polarity transmitted between the two output rails, t2 and r2. binary 0s are transmitted as null pulses. the output pulse waveform is nominally rectangular. the pulses are produced by a high-speed d/a converter and are driven onto the line by low-impedance output buffers. the positive and negative pulses meet ccitt specification g.703 template requirements. the normalized pulse template is shown in figure 5. a block diagram of the analog circuitry is shown in figure 6. the clock multiplier shown in figure 6. uses a phase-locked loop (pll) to produce the high-speed timing waveforms needed to produce a well-controlled pulse width. the clock multiplier also eliminates the need for the tightly.controlled transmit clock duty cycle usually required in discrete implementations. transmitter specifications are shown in the electrical characteristics table. figure 5. ccitt g.703 pulse template 20% 488ns (244 + 244) 219ns (244 - 25) 0% 50% v = 100% 269ns (244 + 25) 194ns (244 - 50) nominal pulse 244ns 10% 10% 10% 10% 10% 10% 20% 20% note: v corresponds to the nominal peak value
XR-T7288 11 rev. 1.01 figure 6. XR-T7288 analog block diagram analog signal detector receiver analog input pdata ndata m u x data/clock recovery rp rn rclk digital signal detector transmit and receive logic tclk tp tn clock multiplier 2 timing signals high speed d/a zs transmit output drivers t1 r1 t2 r2 rdata/rpdata vio/rndata rclk tdata/tpdata hdb3/tndata tclk lp1 los sd receive converter the receive converter accepts bipolar input signals (t1, r1), with a maximum of 6db loss at 1024khz, through the interconnection cable. the received signal is rectified while the amplitude and rise time are restored. these input signals are peak-detected and sliced by the receiver front end, producing the digital signals pdata and ndata (see figure 6. ) receive decision levels are automatically adjusted to be 50% of peak-to-zero signal levels. the timing is extracted by means of pll circuitry that locks an internal, free-running, current-controlled oscillator (ico) to the 2.048mhz component. the pll employs a 3-state phase detector and a low-voltage/temperature coefficient ico. the ico free-running frequency is trimmed to within 2.5% of the data rate at wafer probe, with v dd = 5.0 v and ta = 25 c. for all operating conditions (see operating conditions section), the free-running oscillator frequency deviates from the data rate by less than 7%, alleviating the problem of harmonic lock. for robust operation, the pll is augmented with a frequency-acquisition capability. this feature detects if the recovered pll clock (rclk) deviates by more than +1.7/-1.6% in frequency from a 2.048 mhz reference clock, which must be provided at bclk. if the rclk frequency is not within the prescribed range of the bclk frequency, the XR-T7288 device enters a training mode in which receive input data is disconnected from the pll, and the rclk frequency is steered to equal the bclk frequency. after frequency acquisition is completed, the pll reconnects to receive input data to acquire proper phase-lock and timing of rclk with respect to the incoming t1, r1 data. valid data is available when proper phase-lock has been achieved. the frequency acquisition circuitry is intended to avoid improper harmonic locking during start-up situations, such as power-up or data interruption. once the XR-T7288 device is phase-locked to data, the frequency-acquisition mode will not be activated.
XR-T7288 12 rev. 1.01 a continuous (i.e., ungapped, unswitched) 2.048 mhz reference clock must be present at bclk to enable the frequency-acquisition circuitry. however, the receive pll will operate even in the absence of a 2.048 mhz clock at bclk. the 2.048 mhz clock at tclk can also be used to provide the 2.048 mhz reference at bclk. because the clock output of the receive converter is derived from the ico, a free-running clock can be present at the output of the receive converter without data being present at the input. a shutdown pin (sd) is provided to block this clock, if desired, to eliminate the free-running clock upon loss of the input signal. both analog and digital methods of loss of signal detection are used in the XR-T7288 device. the analog signal detector shown in figure 6. uses the output of the receiver peak detector to determine if a signal is present at t1 and r1. if the input amplitude drops below 0.25 v, typical, the analog detector output becomes active. analog loss-of-signal is registered, at most, several milliseconds after a drop in signal level, depending on a variety of factors, such as initial signal amplitude. hysteresis (140 mv, typical) is provided in the analog detector to eliminate los chattering. the digital signal detector counts 0s in the recovered data. if more than 32 consecutive 0s occur, the digital signal detector becomes active. in normal operation, the detector outputs are ored together to form los ; however, in loopback 1, only the digital signal detector is used to monitor the looped signal. table 2 describes the operation of the shutdown, los , and loc functions in normal operation and in loopback 1. the pll is designed to accommodate large amounts of input jitter with high power supply rejection for operation in noisy environments. low jitter sensitivity to power supply noise allows compact line-card layouts that employ many line interfaces on one board. the minimum input jitter tolerance, as specified in ccitt specification g.823, and the measured XR-T7288 device jitter tolerance are shown in figure 7. receiver specifications are shown on page 4. the XR-T7288 device satisfies the ccitt jitter transfer function requirement of recommendations g.735 g.739 (see figure 8. ) inputs outputs receive side lp1 sd almt input signal at t1, r1 loopback 1 signal los loc receive data 1 rclk 1 active los detectors 1 0 1 active x 1 1 normal normal analog & digital 1 0 1 no signal x 0 1 low 2 free-running ico 2 analog & digital 1 1 1 active x 1 1 normal normal analog & digital 1 1 1 no signal x 0 0 low 3 high analog & digital 0 0 1 x active 1 1 normal loopback normal loopback digital only 0 0 1 x no signal 0 1 low 4 free-running ico 4 digital only 0 1 1 x active 1 1 normal loopback normal loopback digital only 0 1 1 x no signal 0 0 low high digital only x x 0 x x 0 0 unaffected unaffected x notes: 1 these values apply for single-rail or dual-rail/logic mode 1. for dual-rail/logic mode 2, all logic-level outputs except for l ooped back data are the inverse of that shown above. 2 activated by analog loss-of-signal (los) detection. 3 digital los detection forces receive data low . analog los detection merely forces receive data to stop transitions; receive data will be forced either high or low with analog los detection. 4 all-0s looped back data, no hdb3 operation. sufficiently sparse looped back data (not hdb3 encoded) also causes the receive ico to free run; therefore, properly timed loopback data is not guaranteed. table 2. shutdown los and loc truth~table x = don't care.
XR-T7288 13 rev. 1.01 ???????????? ???????????? ???????????? ???????????? ???????????? ???????????? ???????????? 1 0.1 10 100 1k 10k 100k (100k, 0.2) (18k, 0.2) (2.4k, 1.5) (20, 1.5) g.823 specification (1, 2.9) 10 1 XR-T7288 measured performance ber = 1e-6 jitter frequency (hz) input jitter amplitude (u.i. peak-to-peak) note : measurement conditions random data, ta = 25 c, v dd = 5v, 6db cable loss, bclk clock present jitter jitter jitter jitter frequency amplitude frequency amplitude (khz) (u.i. pp) (khz) (u.i. pp) 4 2.00 40 0.45 8 1.06 50 0.44 10 0.87 60 0.43 15 0.65 70 0.44 20 0.52 100 0.51 30 0.46 figure 7. random input data jitter tolerance (hdb3 encoded) figure 8. receive jitter transfer function ???????????????? ???????????????? ???????????????? ???????????????? ???????????????? ???????????????? ???????????????? ???????????????? ???????????????? ???????????????? ???????????????? ???????????????? ???????????????? ???????????????? ???????????????? ???????????????? ???????????????? ???????????????? ???????????????? ???????????????? ???????????????? ???????????????? ???????????????? ???????????????? ???????????????? ???????????????? ???????????????? ???????????????? 0 -5 -10 -15 -20 0.1 1 10 100 36 frequency (khz) 20 log (jout/jin) (db) note: equivalent binary content of input signal: 1000. jitter input amplitude = 0.1 u.i. peak-to-peak. XR-T7288 measured performance (100k, 8.4db) 20db/decade (36k, 0.5db) g.735g.739 specification
XR-T7288 14 rev. 1.01 digital logic the logic provides alarms, optional hdb3 coding, blue signal (ais) insertion circuits, and maintenance loopbacks. it also optionally performs dual-rail to single-rail conversion of the data and provides an alternate logic polarity (logic mode 2) in dual-rail mode for receive clock and receive and transmit data. single-rail/dual-rail interface and alternate logic mode the XR-T7288 device supports either single-rail or dual-rail operation by setting the control pin sr /dr. in the single-rail mode (sr /dr = 0), the XR-T7288 receiver converts bipolar input signals (t1, r1) to a unipolar output signal on rdata. the XR-T7288 transmitter converts a unipolar input signal on tdata to a balanced bipolar data signal on pins t2 and r2. if desired, the hdb3 control pin can be used to set hdb3 encoding/decoding. violation information is available on output pin vio. in the dual-rail mode (sr /dr = 1), the XR-T7288 receiver converts bipolar input signals (t1, r1) to p-rail and n-rail, nonreturn-to-zero output data on pins rpdata and rndata, respectively. the XR-T7288 transmitter converts non-return-to-zero p-rail and n-rail input data on pins tpdata and tndata, respectively, to a balanced bipolar data signal on pins t2 and r2. in the dual-rail mode, hdb3 encoding/decoding and bipolar violation output functions are unavailable. in the dual-rail mode, an alternate-logic polarity mode is available via control pin flm. if flm = 1, the XR-T7288 device operates in logic mode 2; rclk is inverted with respect to logic mode 1, and input and output data (tpdata, tndata, rpdata, and rndata) are active-low (see figures 10-13 ). internal pull-downs on signals sr /dr and flm set default operation to single-rail, logic mode 1 (see table 3 ) flm sr /dr single-/dual-rail logic mode 0 1 0 1 single 1 0 1 dual 1 1 0 x 2 x 2 1 1 dual 2 notes: 1 default operation (identical with lc1135b) if both pins are unconnected. 2 x = illegal option table 3. rail interface and logic mode options pin name function 3 hdb3/tndat hdb3 enable 4 vio/rndata vio violation 6 rdata/rpdata rdata receive data 8 tdata/tpdata tdata transmit data table 4. single-rail operation (default state) sr /dr = 0 (or left unconnected internal pull-down circuitry). pin name function 3 hdb3/tndata n-rail transmit input data 4 vio/rndata n-rail receive output data 6 rdata/rpdata p-rail receive output data 8 tdata/tpdata p-rail transmit input data table 5. dual-rail operation sr /dr = 1
XR-T7288 15 rev. 1.01 alarms an independent loss-of-clock (loc ) output is provided so that loss of clock is detected when the shutdown option is in effect. los and loc can be wire-ored to produce a single alarm. a bipolar violation output is included if hdb3 = 0, giving an alarm (vio) each time a violation occurs (two or more successive 1s on a rail). the violation alarm output is held in a latch for one cycle of the internal clock (rclk). in the hdb3 mode, hdb3 code violations are detected and an alarm is produced. an alarm test pin (almt ) is provided to test the alarm outputs, los , loc and vio. clearing this pin forces the alarm outputs to the alarm state without affecting data transmission. hdb3 option the XR-T7288 device contains an hdb3 encoder and decoder (for single-rail mode only, i.e., sd /dr = 0) that can be selected by setting the hdb3 pin. this allows the encoder to substitute a zero-substitution code for four consecutive 0s detected in the data stream, as illustrated in table 6 a avo represents a violation of the hdb3 code, and a abo represents a bipolar pulse of correct polarity. the decoder detects the zero-substitution code and reinserts four 0s in the data stream. case 1: preceding mark has a polarity opposite the polarity of the preceding violation and is not a violation itself. case 2: preceding mark has a polarity the same as the polarity of the preceding violation or is a violation itself. case 1 case 2 before hdb3 0000 0000 after hdb3 000v b00v table 6. hdb3 substitution code blue signal (ais) generators there are two blue signal (ais) generators in this device. one (rbc = 1) substitutes an all-1s signal on rdata output (sr /dr = 0) or rpdata and rndata (sr /dr = 1) toward the terminal equipment. the other (tbc = 1) substitutes a bipolar, all-1s signal for the bipolar data out of the transmit converter which can be used to keep line repeaters active. loopback paths the XR-T7288 device has three independent loopback paths that are activated by clearing the respective control inputs, lp1 , lp2 or lp3 . loopback 1 bridges the data stream from the transmit converter (transmit converter included) to the input of the receive converter. this maintenance loop includes most of the internal circuitry. loopback 2 provides a loopback of data and recovered clock from the bipolar inputs (t1, r1) to the bipolar outputs of the transmit converter (t2, r2). the receive front end, receive pll, and transmit driver circuitry are all exercised. the loop can be used to isolate failures between systems. tbc = 1 overrides this function. loopback 3 loops the data stream as in loopback 1 but bypasses the transmit and receive converters. the blue signal (ais) can be transmitted to the line when in this loopback. loopbacks 2 and 3 can be operated simultaneously to provide transmission loops in both directions. current pulses with all other pins grounded, current pulses of maximum value and time widths are allowed on the t1/r1 and t2/r2 pins without damaging the device, as shown in table 7 . also, to help ensure long-term reliability, the average value of a current-pulse train is specified. pin max value width avg value t1, r1 20 ma 1 m s to 1s 6 ma t2, r2 200 ma 1 m s to 1s 40 ma table 7. maximum allowable current
XR-T7288 16 rev. 1.01 handling precautions although protection circuitry has been designed into this device, proper precautions should be taken to avoid exposure to electrostatic discharge (esd) during handling and mounting. exar employs a human-body model (hbm) and a charged-device model (cdm) for esd-susceptibility testing and protection design evaluation. esd voltage thresholds are dependent on the circuit parameters used to define the model. no industry-wide standard has been adopted for the cdm. however, a standard hbm (resistance = 1500, capacitance = 100 pf) is widely used and, therefore, can be used for comparison purposes. the hbm esd threshold presented here was obtained by using these circuit parameters: hbm esd threshold device voltage XR-T7288 >2500 v table 8. ???? ???? ???? ???? ???? ???? ?? ?? ?? ?? ?? ?? ?? ??????? ??????? ??????? ??????? ??????? ??????? regulated high voltage power supply ????? ????? ????? ????? ????? ? ? ? ? ? ???? ???? ???? ???? ???? ???? ?? ?? ?? ?? ?? ?? ?? c1 for device testing r2 rl1 r1 p1 socket notes: p1 ? 0kv to 5kv dc power supply. r1 ? at least 10 m w , high-voltage, 1w carbon composition. rl1 ? high-voltage (5 kv) relay of a bounceless type (mercury-wetted or equivalent). c1 ? 100pf, 5kv capacitor. r2 ? 1500 w 5%, 1w carbon composition < 1pf shunt capacitance. figure 9. circuit schematic of human-body esd simulator ?? ?? ?? ?? ?? ?? ?? ?? ?? ??
XR-T7288 17 rev. 1.01 timing characteristics all dutycycle and timing relationships are in reference to a ttl, 1.4v threshold level. lossofclock indication timing the clock must be absent 6.4 s to guarantee a lossofclock indication.however, a lossofclock indication can occur if the clock is absent for as little as 1.95 m s, depending on the timing relationship of the interruption with respect to the timing cycle. the returning clock must be present 3.91 m s to guarantee a normal condition on the lossofclock pin (loc). however, the lossofclock indication can return to normal immediately, depending on the timing relationship of the signal return with respect to the timing cycle. t a = 40 c to 85 c; v dd = 5 v 10%; load capacitance = 40 pf. symbol description min typ max unit ttcltcl tclk clock period 1 488 1 ns ttchtcl tclk duty cycle 40 50 60 % ttdvtcl data setup time, tdata 2 to tclk 50 ns ttcltdv data hold time, tclk to tdata 2 40 ns tr clock rise time (10% 90%) 40 ns tf clock fall time (10% 90%) 40 ns trclrcl rclk duty cycle 40 50 60 % trchrdv data hold time, rclk to rdata, vio 3 171 ns trdvrch data setup time, rdata, vio to rclk 3 131 ns trclrdv propagation delay, rclk to rdata, vio 3 40 ns table 9. clock timing relationships notes 1 a tolerance of 80 ppm. 2 data for singlerail mode; tpdata and tndata for dualrail mode. 3 rdata and vio for singlerail mode; rpdata and rndata for dualrail mode.
XR-T7288 18 rev. 1.01 timing diagrams (single-rail or dual-rail, logic mode 1) ttcltcl tr tf tclk (tc) tdata or tpdata tndata (td) ttdvtcl figure 10. transmit timing ttcltdv trclrdv tr tf rclk (rc) rdata vio or rpdata rndata (rd) figure 11. receive timing trdvrch trchrdv
XR-T7288 19 rev. 1.01 timing diagrams (dual-rail, logic mode 2) ttcltcl tr tf tclk (tc) tpdata tndata (td) ttdvtcl figure 12. transmit timing ttcltdv trclrdv tr tf rclk (rc) rdata vio or rpdata rndata (rd) figure 13. receive timing trdvrch trchrdv active low ?? ?? ?? ?? active low
XR-T7288 20 rev. 1.01 transformer requirements turns ratio line impedance r load 1:1 75 w 75 w 1:1 120 w 120 w 1:1 100 w 100 w table 10. input transformer requirements turns ratio line impedance r out 1:1 75 w 68 w 1:1.265 120 w 68 w 1:1.265 100 w 62 w table 11. output transformer requirements magnetic supplier information: pulse telecom product group p.o. box 12235 san diego, ca 92112 tel. (619) 674-8100 fax. (619) 674-8262 transpower technologies, inc. 24 highway 28, suite 202 crystal bay, nv 894020187 tel. (702) 8310140 fax. (702) 8313521
XR-T7288 21 rev. 1.01 28 lead plastic dual-in-line (300 mil pdip) rev. 1.00 symbol min max min max inches a 0.145 0.210 3.68 5.33 a 1 0.015 0.070 0.51 1.78 a 2 0.115 0.195 2.92 4.95 b 0.014 0.024 0.36 0.56 b 1 0.030 0.070 0.76 1.78 c 0.008 0.014 0.20 0.38 d 1.345 1.400 34.16 35.56 e 0.300 0.325 7.62 8.26 e 1 0.265 0.310 7.11 7.49 e 0.100 bsc 2.54 bsc e a 0.300 bsc 7.62 bsc e b 0.310 0.430 7.87 10.92 l 0.115 0.150 2.92 3.81 a 0 15 0 15 millimeters 28 1 15 14 d e a 1 e 1 a l seating plane e a 2 a b 1 b c note: the control dimension is the inch column e b e a
XR-T7288 22 rev. 1.01 28 lead small outline j lead (300 mil jedec soj) rev. 1.00 e d e h b a 1 seating plane 28 15 14 1 a 2 symbol min max min max a 0.145 0.200 3.60 5.08 a 1 0.025 0.64 a 2 0.120 0.140 3.05 3.56 b 0.014 0.020 0.36 0.51 c 0.008 0.013 0.20 0.30 d 0.697 0.712 17.70 18.08 e 0.292 0.300 7.42 7.62 e 1 0.262 0.272 6.65 6.91 e 0.050 bsc 1.27 bsc h 0.335 0.347 8.51 8.81 r 0.030 0.040 0.76 1.02 inches millimeters note: the control dimension is the inch column a c r e 1
XR-T7288 23 rev. 1.01 notes
XR-T7288 24 rev. 1.01 notice exar corporation reserves the right to make changes to the products contained in this publication in order to im- prove design, performance or reliability. exar corporation assumes no responsibility for the use of any circuits de- scribed herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. charts and schedules contained here in are only for illustration purposes and may vary depending upon a user's specific application. while the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. exar corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. products are not authorized for use in such applications unless exar corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of exar corporation is adequately protected under the circum- stances. copyright 1992 exar corporation datasheet june 1997 reproduction, in part or whole, without the prior written consent of exar corporation is prohibited.

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